Non-volatile dynamic random access memory (NVDRAM)

ABSTRACT

A NVDRAM includes a first NV element coupled to a first terminal of a second NV element at a transfer node. A volatile cell has a transfer transistor coupled to the transfer node and has a storage node. A first NV line is coupled to the second terminal of the first NV element. Circuitry applies an alternated signal to the transfer node, couples the second terminal of the second non-volatile element to a second NV line, and applies a program signal across the first and second NV lines during a program mode that establishes a logic state. The circuitry applies a read signal across the first and second NV lines, couples the second terminal of the second NV element to the second NV line, and replaces the alternated signal with floating during a restore mode that loads the logic state into the storage node.

BACKGROUND

1. Field

This disclosure relates generally to integrated circuits, and moreparticularly, to non-volatile dynamic random access memories (NVDRAMs).

2. Related Art

Non-volatile memories (NVMs) have become very important in a variety ofapplications but NVMs typically are slower than other types of memories.Thus it is common to have both NVMs and random access memories (RAMs) onthe same integrated circuit because normal operations typically do notrequire the non-volatile feature. One approach is to combine thenon-volatile feature with RAM characteristics. For example, thenon-volatile feature is used rarely, such as at power-up and power-down,and the RAM characteristic is used otherwise. The RAM characteristic canbe for both interfacing with non-volatile feature for simply a portionof the general purpose RAM. Often the RAM is a static RAM (SRAM), but itcan be beneficial for the RAM to be a dynamic RAM (DRAM) due to thesmaller size. If general purpose DRAM is going to be present on theintegrated circuit anyway, then the use of DRAM cells in combinationwith NVM cells may be more efficient due to the smaller size than usingSRAMs in combination with the NVM cells. Arranging a memory that hasboth the DRAM characteristic and the NVM characteristic in a manner thatis effective in reliably achieving the desired operating characteristicswithout requiring excessive space has been found to be challenging.

Accordingly there is a need to provide further improvement in obtainingNVDRAMs.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and is notlimited by the accompanying FIGURES, in which like references indicatesimilar elements. Elements in the FIGURES are illustrated for simplicityand clarity and have not necessarily been drawn to scale.

The FIGURE is a circuit diagram of a non-volatile dynamic random accessmemory (NVDRAM) memory array.

DETAILED DESCRIPTION

In one aspect, a non-volatile dynamic random access memory cell has acapacitor coupled to a storage node located between two transistors. Oneof the transistors is coupled to a volatile bit line and the othertransistor is coupled to a transfer node located between twonon-volatile elements that are coupled together at the transfer node.The two non-volatile elements are selectively programmed to oppositeresistive states by coupling the transfer node to a selected voltagewhile coupling the other terminals of the non-volatile elements to adifferent selected voltage. The resulting opposing resistive statesdefine a logic state at the transfer node that, when it is desired toread the logic state, is coupled to the storage node where it isselectively coupled to the volatile bit line. This is better understoodby reference to the drawings and the following written description.

Shown in the FIGURE is non-volatile dynamic random access memory(NVDRAM) 100 having an array 102 having NVDRAM cells 104, 106, 108, and110; a column decoder control 112; a column multiplexer 114; an outputcircuit 116; an input circuit 117, an output circuit 118, an inputcircuit 119; a row decoder 120; a bit line BL0, a non-volatile line NV0,a non-volatile line NV′0, a bit line BL1, a non-volatile line NV1, anon-volatile line NV′1, a word line WL0, a word line WL1, a select lineSEL0, a select line SEL1, a line COM0, and a line COM1. NVDRAM cell 104comprises a transistor 122, a capacitor 124, a transistor 126, anon-volatile element 128, a non-volatile element 130, a transistor 132,and a transistor 134. Non-volatile elements 128 and 130 may bemagnetoresistive tunnel junctions (MTJ) which is the non-volatileelement commonly used in MRAMs. NVDRAM cells 106, 108, and 110 have thesame elements that are connected the same as NVDRAM 104 except for beingconnected to a unique combination of word lines, select lines,non-volatile lines, and bit lines. NVDRAM cells 106, 108, and 110comprise a transistor 136, 150, and 164, respectively; a capacitor 138,152, and 166, respectively; a transistor 140, 154, 168, respectively; anon-volatile element 142, 156, and 170, respectively; a non-volatileelement 144, 158, and 172, respectively; a transistor 146, 160, and 174,respectively, and a transistor 148, 162, and 176, respectively.

Using NVDRAM 104 as the example for NVDRAMs 106, 108, and 110, as wellas many other NVDRAMs not shown, transistor 122, which may be N channel,has a first current electrode connected to bit line BL0, a controlelectrode coupled to word line WL0, and a second current electrodecoupled to a node A. Capacitor 124 has a first terminal connected tonode A and a second terminal connected to a reference voltage Vref,which may be ground. Capacitor 124 and transistor 122 together form aDRAM cell 121. Transistor 126, which may be N channel, has a firstcurrent electrode which is the source in this case, connected to ground,a second current electrode coupled to node A, and a gate connected to anode B. Non-volatile element 128 has a first terminal connected to nodeB and a second terminal connected to line NV′0. Non-volatile element 128is formed in a direction in which it is written to a higher resistancewhen current flows from node B to line NV′0 and to a lower resistancewhen current flows from line NV′0 to node B. Non-volatile element 130has a first terminal connected to node B and a second terminal connectedto transistor 134. Non-volatile element 130 is formed in a direction inwhich it is written to a higher resistance when current flows from nodeB to line NV0 and to a lower resistance when current flows from line NV0to node B. Transistor 134, which may be N channel, has a first currentelectrode connected to the second terminal of non-volatile element 130,a gate connected to select line SEL0 and to the gate of transistor 132,and a second current electrode connected to line NV0. Transistor 132,which may be N channel, has a first current electrode connected to nodeB, a gate connected to select line SEL0, and a second current electrodeconnected to line COM0.

The gates of transistors 136, 150, and 164, which are analogous totransistor 122, are connected to word lines, WL1, WL0, and WL1,respectively. The gates of transistors 146, 160, and 174, which areanalogous to transistor 132, are connected to line SEL1, line SEL0, andline SEL1, respectively. The gates of transistors 148, 162, and 176,which are analogous to transistor 134, are connected to line SEL1, lineSEL0, and line SEL1, respectively. The second current electrodes oftransistors 146, 160, and 174 are connected to line COM0, COM1, andCOM1, respectively. The second current electrodes of transistors 148,162, and 176 are connected to line NV0, line NV1, and line NV1,respectively. The second terminals of non-volatile elements 142, 156,and 170, which are analogous to non-volatile element 128, are connectedto line NV′0, line NV′1, and line NV′1, respectively.

Operation of NVDRAM cells 104, 106, 108, and 110 includes reading,writing, store, and restore. Using NVDRAM as an example, reading, inresponse to column decoder control 112 receiving a read signal, isachieved by row decoder 120 asserting a logic high on word line WL0,selected by the row portion of the address, which causes transistor 122to become conductive which couples node A to bit line BL0 so that thelogic state of node A is thereby coupled to bit line BL0. Column decodercontrol 112 couples bit line BL0 as selected by a portion of the columnaddress to column multiplexer 114. Column multiplexer 114 then couplesbit line BL0 to output circuit 116, as selected by another portion ofthe column address, which compares the signal present on bit line BL0 toa reference REF and provides a logic high output as output signal DATA0if bit line BL0 is a logic high and a logic low if bit line BL0 is alogic low. Column decoder control 112 and column multiplexer 114 mayprovide sensing and buffering of the signal present on bit line BL0prior to amplifier 116 receiving it. Writing into NVDRAM cell isachieved by writing into node A of DRAM cell 121 by reversing theprocess of reading. An input signal DIN0 is received by input circuit117 where it is routed to bit line BL0 by column multiplexer 114 andcolumn decoder control 112 as selected by the column portions of theaddress. Word line WL0 is asserted with a logic that causes transistor122 to be conductive which results in bit line 0 being coupled to node Aso that logic state present on bit line BL0 becomes present on node A ofNVDRAM cell 104. During normal read and write operations, line COM0 isfloating, line SEL1 is a logic low so that transistors 132 and 134 arenon-conductive, lines NV0 and NV′0 are both at a logic low ensuring thatcurrent does not pass through non-volatile elements 128 and 130. Withline NV′0 at a logic low and transistors 132 and 134 beingnon-conductive, node B is held at a logic low. Node B at a logic lowensures that transistor 126 is non-conductive.

For a store operation in the logic state of DRAM 121 is to be stored innon-volatile elements 128 and 130, DRAM cell 121 is read as previouslydescribed but word line WL0 is not subsequently asserted during thestore operation so that the gate of transistor 122 receives a logic lowand is non-conductive and node A is decoupled from bit line BL0. Also,the another logic state from that present in DRAM cell 121 may be whatis to be stored. For writing a logic low, line NV0 is at a logic high asapplied by column decoder control 112, line NV′0 is at a logic low asapplied by column decoder control 112, and line SEL0 is at a logic highas applied by column decoder control 112. For the programming to occur,line COM0 is initially at an intermediate voltage between a logic lowand a logic high or at a high impedance, state and then switches betweenone logic state then the other which can be either logic low followed bylogic high or logic high followed by logic low. When a logic high isapplied, the logic high is coupled through transistor 132 to node B.With a logic high on node B and a logic low on line NV′0, current flowsin the direction through non-volatile element 128 that causes it to bein the relatively high resistance state. No current is flowing throughnon-volatile element 130 because both line NV0 and node B are at a logichigh. When line COM0 switches to the logic low state, node B becomes alogic low, so that current flows from line NV0 through transistor 134and non-volatile element 130 to node B causing non-volatile element 144to be in the relatively low resistance state. Line COM0 is then switchedback to either the high impedance state or the intermediate state. Thusthe logic low is achieved with two non-volatile elements in opposingresistive states to obtain a greater variation with voltage divisionthan using only one non-volatile element in combination with a fixedresistive element.

For storing a logic low, either the timing of the logic high and logiclow is reversed for line COM0 or with lines NV0 and NV′0 from that usedfor storing the logic high. In the case of keeping the timing of lineCOM0 the same, line NV′0 is initially a logic high and line NV0 is alogic low. When line COM0 is applied at a logic high, node B is a logichigh, and current flows from node B to line NV0 causing non-volatileelement 130 to become relatively high resistance. With line NV′0 andnode B at a logic low, no current flows through non-volatile element128.l Line COM0 then switches to a logic low causing current to flowfrom line NV′0 to node B which causes non-volatile element 128 to be inits relatively low resistance state. No current flows throughnon-volatile element 130 because node B and line NV0 are at a logic low.As for the logic low case, the logic high is achieved with onenon-volatile element at its relatively low resistive state while theother is at its relatively high resistive state which also provides fora favorable voltage division as compared to having only one non-volatileelement with a fixed resistive element.

For a restore operation in which the logic state established by thenon-volatile elements, is coupled to DRAM cell 121, DRAM cell 121 iswritten to a logic high, and then transistor 122 is kept non-conductive.Line COM0 is kept floating by no signal being applied by column decodercontrol 112, line SEL0 is applied at a logic high causing transistors132 and 134 to be conductive, line NV0 is applied at a restore voltage,and line NV′0 is applied at a logic low. For the case of non-volatileelements being at a logic low, non-volatile elements 128 and 130 are atthe relatively high resistance and relatively low resistancerespectively. The conversion of node A from the logic high initialcondition to the logic low condition is achieved by the voltage at nodeB being sufficient to ensure that transistor 126 becomes sufficientlyconductive to convert node A from a logic high to a logic low. For thelogic high case of non-volatile elements 128 and 130 being relativelylow resistance and relatively high resistance, respectively, transistor126 is kept non-conductive so as not to disturb the logic high presenton node A. The magnitude chosen for the restore voltage is optimized toachieve this desired result of transistor 126 successfully convertingnode A to a logic low when for the logic low restore and keepingtransistor 126 sufficiently non-conductive to keep node A at the logichigh sufficiently long so as to be subsequently successfully refreshed.

Thus it is seen that even with relatively small differences between arelatively high resistance and a relatively low resistance, using twonon-volatile elements can be effective in obtaining a more robust logichigh and logic low.

By now it should be appreciated that there has been disclosed anon-volatile dynamic random access memory (NVDRAM), including a firstbit line; a first non-volatile line; a second non-volatile line; a firstselect line; and a first NVDRAM cell. The first NVDRAM includes a firstDRAM cell, coupled to the first bit line. The first DRAM includes afirst capacitor having a first terminal coupled to a first storage nodeand a second terminal coupled to a reference and a first transfertransistor having a first current electrode coupled to a first powersupply terminal, a second current electrode coupled to the first storagenode, and a control electrode. The first NVDRAM further includes a firstpass gate transistor coupled between the first bit line and the firststorage node. The first NVDRAM further includes a first non-volatileelement having a first terminal coupled to the control electrode of thefirst transfer transistor and a second terminal coupled to the firstnon-volatile line. The first NVDRAM further includes a secondnon-volatile element having a first terminal coupled to the controlelectrode of the first transfer transistor and a second terminal. Thefirst NVDRAM further includes a first switching transistor having afirst current electrode for receiving a first program signal, a secondcurrent electrode coupled to the control electrode of the first transfertransistor, and a control electrode coupled to the first select line.The first NVDRAM further includes a second switching transistor having afirst current electrode coupled to the second terminal of the secondnon-volatile element, a second current electrode coupled to the secondnon-volatile line, and a control electrode coupled to the first selectline. The NVDRAM may have a further characterization by which the NVDRAMfurther comprises a first word line, wherein the first pass gatetransistor has a control electrode coupled to the first word line. TheNVDRAM may have a further characterization by which the firstnon-volatile element comprises a first programmable resistor. The NVDRAMmay have a further characterization by which the first programmableresistor comprises a RRAM resistor. The NVDRAM may have a furthercharacterization by which the programmable resistor comprises a STT-RAMMTJ. The NVDRAM may further include a second bit line, a fourthnon-volatile line, and a second NVDRAM cell coupled to the first bitline. The second NVDRAM cell may further include a second DRAM cell. Thesecond DRAM cell may further include a second capacitor having a firstterminal coupled to a second storage node and a second terminal coupledto the reference and a second transfer transistor having a first currentelectrode coupled to the first power supply terminal, a second currentelectrode coupled to the second storage node, and a control electrode.The second NVDRAM cell may further include a second pass gate transistorcoupled between the second bit line and the second storage node. Thesecond NVDRAM cell may further include a fourth non-volatile elementhaving a first terminal coupled to the control electrode of the secondtransfer transistor and a second terminal. The second NVDRAM cell mayfurther include a fourth switching transistor having a first currentelectrode coupled to the second terminal of the fourth non-volatileelement, a second current electrode coupled to the fourth non-volatileline, and a control electrode coupled to the first select line. Thesecond NVDRAM cell may further include a third switching transistorhaving a first current electrode for receiving a second program signal,a second current electrode coupled to the control electrode of thesecond transfer transistor, and a control electrode coupled to the firstselect line. The second NVDRAM cell may further include a fourthswitching transistor having a first current electrode coupled to thesecond terminal of the fourth non-volatile element, a second currentelectrode coupled to the fourth non-volatile line, and a controlelectrode coupled to the first select line. The NVDRAM may have afurther characterization by which the NVDRAM further comprises a firstword line, wherein the first pass gate transistor has a controlelectrode coupled to the first word line and the second pass gatetransistor has a control electrode coupled to the first word lin. TheNVDRAM may further include a second select line, a third NVDRAM cell,and a third DRAM cell in which the third DRAM cell is coupled to thefirst bit line and includes a third capacitor having a first terminalcoupled to a third storage node and a second terminal coupled to thereference and a third transfer transistor having a first currentelectrode coupled to the first power supply terminal, a second currentelectrode coupled to the third storage node, and a control electrode.The third NVDRAM may further include a third pass gate transistorcoupled between the first bit line and the third storage node. The thirdNVDRAM may further include a fifth non-volatile element having a firstterminal coupled to the control electrode of the third transfertransistor and a second terminal coupled to the first non-volatile line.The third NVDRAM may further include a sixth non-volatile element havinga first terminal coupled to the control electrode of the third transfertransistor and a second terminal. The third NVDRAM may further include athird switching transistor having a first current electrode forreceiving the first program signal, a second current electrode coupledto the control electrode of the third transfer transistor, and a controlelectrode coupled to the second select line. The third NVDRAM mayfurther include a fourth switching transistor having a first currentelectrode coupled to the second terminal of the fourth non-volatileelement, a second current electrode coupled to the fourth non-volatileline, and a control electrode coupled to the second select line. TheNVDRAM may have a further characterization by which the NVDRAM furthercomprises a first word line and a second word line, wherein the firstpass gate transistor has a control electrode coupled to the first wordline, the second pass gate transistor has a control electrode coupled tothe first word line, and the third pass gate transistor has a controlelectrode coupled to the second word line. The NVDRAM may furtherinclude a first decoder coupled to the first bit line, the second bitline, the first non-volatile line, the second non-volatile line, thethird non-volatile line, and a fourth non-volatile line. The NVDRAM mayfurther include a multiplexer coupled to the first decoder for providingoutput data. The NVDRAM may further include a row decoder coupled to thefirst word line, the second word line, the first select line, and thesecond select line.

Also disclosed is a method of operating a non-volatile dynamic randomaccess memory (NVDRAM) cell having a first non-volatile element having afirst terminal coupled to a first terminal of a second non-volatileelement at a transfer node, the first and second non-volatile elementshaving second terminals including programming the first non-volatileelement and the second non-volatile element by applying a voltagedifferential to the second terminals of the first and secondnon-volatile elements while providing an alternated voltage at thetransfer node to result in a logic state represented by a resistancedifferential between the first non-volatile element and the secondnon-volatile element. The method further includes transferring the logicstate to a storage node through a transfer transistor coupled to thetransfer node and the storage node. The method further includes readingthe logic state by coupling the storage node to a bit line through apass gate transistor. The method may have a further characterization bywhich the programming is further characterized by the voltagedifferential being applied across a first non-volatile line and a secondnon-volatile line, the second terminal of the first non-volatile elementbeing coupled to the first non-volatile line, and the second terminal ofthe second non-volatile element being coupled to the second non-volatileline and the alternated voltage being applied to the to the transfernode in response to a program signal being enabled. The method may havea further characterization by which the transferring is furthercharacterized by applying a restore signal across the first non-volatileline and the second non-volatile line while coupling the second terminalof the second non-volatile element to the second non-volatile line. Themethod may have a further characterization by which the transferring isfurther characterized by a control electrode of the transfer transistorbeing coupled to the transfer node. The method may have a furthercharacterization by which, during the transferring, the alternatedvoltage applied during the programming is replaced with floating.

Disclosed also is a non-volatile dynamic random access memory (NVDRAM)including a first non-volatile element having a first terminal coupledto a first terminal of a second non-volatile element at a transfer node,the first and second non-volatile elements having second terminals. TheNVDRAM further includes a DRAM cell having a transfer transistor and astorage node, wherein the transfer transistor is coupled to the storagenode and the transfer node. The NVDRAM further includes a firstnon-volatile line coupled to the second terminal of the firstnon-volatile element and a second non-volatile line. The NVDRAM furtherincludes circuitry that, during a program mode, applies an alternatedsignal to the transfer node, couples the second terminal of the secondnon-volatile element to the second non-volatile line, and applies aprogram signal across the first and second non-volatile lines and that,during a restore mode, applies a read signal across the first and secondnon-volatile lines, couples the second terminal of the secondnon-volatile element to the second non-volatile line, and replaces thealternated signal with floating, in which a logic state represented thefirst and second non-volatile elements that have been programmed isloaded from the transfer node to the storage node. The NVDRAM mayfurther include a pass gate coupled between a bit line and the storagenode that is used to couple the bit line to the storage node thatenables reading the logic state.

Although the invention is described herein with reference to specificembodiments, various modifications and changes can be made withoutdeparting from the scope of the present invention as set forth in theclaims below. For example, the particular type of non-volatile elementcan vary from the disclosed type. Accordingly, the specification andFIGURES are to be regarded in an illustrative rather than a restrictivesense, and all such modifications are intended to be included within thescope of the present invention. Any benefits, advantages, or solutionsto problems that are described herein with regard to specificembodiments are not intended to be construed as a critical, required, oressential feature or element of any or all the claims.

The term “coupled,” as used herein, is not intended to be limited to adirect coupling or a mechanical coupling.

Furthermore, the terms “a” or “an,” as used herein, are defined as oneor more than one. Also, the use of introductory phrases such as “atleast one” and “one or more” in the claims should not be construed toimply that the introduction of another claim element by the indefinitearticles “a” or “an” limits any particular claim containing suchintroduced claim element to inventions containing only one such element,even when the same claim includes the introductory phrases “one or more”or “at least one” and indefinite articles such as “a” or “an.” The sameholds true for the use of definite articles.

Unless stated otherwise, terms such as “first” and “second” are used toarbitrarily distinguish between the elements such terms describe. Thus,these terms are not necessarily intended to indicate temporal or otherprioritization of such elements.

What is claimed is:
 1. A non-volatile dynamic random access memory(NVDRAM), comprising: a first bit line; a first non-volatile line; asecond non-volatile line; a first select line; and a first NVDRAM cell,comprising: a first DRAM cell, coupled to the first bit line,comprising: a first capacitor having a first terminal coupled to a firststorage node and a second terminal coupled to a reference; and a firsttransfer transistor having a first current electrode coupled to a firstpower supply terminal, a second current electrode coupled to the firststorage node, and a control electrode; a first pass gate transistorcoupled between the first bit line and the first storage node; a firstnon-volatile element having a first terminal coupled to the controlelectrode of the first transfer transistor and a second terminal coupledto the first non-volatile line; a second non-volatile element having afirst terminal coupled to the control electrode of the first transfertransistor and a second terminal; a first switching transistor having afirst current electrode for receiving a first program signal, a secondcurrent electrode coupled to the control electrode of the first transfertransistor, and a control electrode coupled to the first select line;and a second switching transistor having a first current electrodecoupled to the second terminal of the second non-volatile element, asecond current electrode coupled to the second non-volatile line, and acontrol electrode coupled to the first select line.
 2. The NVDRAM ofclaim 1, wherein the NVDRAM further comprises a first word line, whereinthe first pass gate transistor has a control electrode coupled to thefirst word line.
 3. The NVDRAM of claim 1, wherein the firstnon-volatile element comprises a first programmable resistor.
 4. TheNVDRAM of claim 3, wherein the first programmable resistor comprises aRRAM resistor.
 5. The NVDRAM of claim 3, wherein the programmableresistor comprises a STT-RAM MTJ.
 6. The NVDRAM of claim 1, furthercomprising: a second bit line; a third non-volatile line; a fourthnon-volatile line; and a second NVDRAM cell, comprising: a second DRAMcell, coupled to the first bit line, comprising: a second capacitorhaving a first terminal coupled to a second storage node and a secondterminal coupled to the reference; and a second transfer transistorhaving a first current electrode coupled to the first power supplyterminal, a second current electrode coupled to the second storage node,and a control electrode; a second pass gate transistor coupled betweenthe second bit line and the second storage node; a third non-volatileelement having a first terminal coupled to the control electrode of thesecond transfer transistor and a second terminal coupled to the thirdnon-volatile line; a fourth non-volatile element having a first terminalcoupled to the control electrode of the second transfer transistor and asecond terminal; a third switching transistor having a first currentelectrode for receiving a second program signal, a second currentelectrode coupled to the control electrode of the second transfertransistor, and a control electrode coupled to the first select line;and a fourth switching transistor having a first current electrodecoupled to the second terminal of the fourth non-volatile element, asecond current electrode coupled to the fourth non-volatile line, and acontrol electrode coupled to the first select line.
 7. The NVDRAM ofclaim 6, wherein the NVDRAM further comprises a first word line, whereinthe first pass gate transistor has a control electrode coupled to thefirst word line and the second pass gate transistor has a controlelectrode coupled to the first word line.
 8. The NVDRAM of claim 6,further comprising: a second select line; and a third NVDRAM cell,comprising: a third DRAM cell, coupled to the first bit line,comprising: a third capacitor having a first terminal coupled to a thirdstorage node and a second terminal coupled to the reference; and a thirdtransfer transistor having a first current electrode coupled to thefirst power supply terminal, a second current electrode coupled to thethird storage node, and a control electrode; a third pass gatetransistor coupled between the first bit line and the third storagenode; a fifth non-volatile element having a first terminal coupled tothe control electrode of the third transfer transistor and a secondterminal coupled to the first non-volatile line; a sixth non-volatileelement having a first terminal coupled to the control electrode of thethird transfer transistor and a second terminal; a third switchingtransistor having a first current electrode for receiving the firstprogram signal, a second current electrode coupled to the controlelectrode of the third transfer transistor, and a control electrodecoupled to the second select line; and a fourth switching transistorhaving a first current electrode coupled to the second terminal of thefourth non-volatile element, a second current electrode coupled to thefourth non-volatile line, and a control electrode coupled to the secondselect line.
 9. The NVDRAM of claim 8, wherein the NVDRAM furthercomprises a first word line and a second word line, wherein the firstpass gate transistor has a control electrode coupled to the first wordline, the second pass gate transistor has a control electrode coupled tothe first word line, and the third pass gate transistor has a controlelectrode coupled to the second word line.
 10. The NVDRAM of claim 9,further comprising: a first decoder coupled to the first bit line, thesecond bit line, the first non-volatile line, the second non-volatileline, the third non-volatile line, and a fourth non-volatile line. 11.The NVDRAM of claim 10, further comprising a multiplexer coupled to thefirst decoder for providing output data.
 12. The NVDRAM of claim 11,further comprising a row decoder coupled to the first word line, thesecond word line, the first select line, and the second select line. 13.A method of operating a non-volatile dynamic random access memory(NVDRAM) cell having a first non-volatile element having a firstterminal coupled to a first terminal of a second non-volatile element ata transfer node, the first and second non-volatile elements havingsecond terminals, comprising: programming the first non-volatile elementand the second non-volatile element by applying a voltage differentialto the second terminals of the first and second non-volatile elementswhile providing an alternated voltage at the transfer node to result ina logic state represented by a resistance differential between the firstnon-volatile element and the second non-volatile element; transferringthe logic state to a storage node through a transfer transistor coupledto the transfer node and the storage node: and reading the logic stateby coupling the storage node to a bit line through a pass gatetransistor.
 14. The method of claim 13, wherein the programming isfurther characterized by the voltage differential being applied across afirst non-volatile line and a second non-volatile line, the secondterminal of the first non-volatile element being coupled to the firstnon-volatile line, and the second terminal of the second non-volatileelement being coupled to the second non-volatile line and the alternatedvoltage being applied to the to the transfer node in response to aprogram signal being enabled.
 15. The method of claim 14, wherein thetransferring is further characterized by applying a restore signalacross the first non-volatile line and the second non-volatile linewhile coupling the second terminal of the second non-volatile element tothe second non-volatile line.
 16. The method of claim 15, wherein thetransferring is further characterized by a control electrode of thetransfer transistor being coupled to the transfer node.
 17. The methodof claim 14, wherein during the transferring, the alternated voltageapplied during the programming is replaced with floating.
 18. Anon-volatile dynamic random access memory (NVDRAM), comprising: a firstnon-volatile element having a first terminal coupled to a first terminalof a second non-volatile element at a transfer node, the first andsecond non-volatile elements having second terminals; a DRAM cell havinga transfer transistor and a storage node, wherein the transfertransistor is coupled to the storage node and the transfer node; a firstnon-volatile line coupled to the second terminal of the firstnon-volatile element and a second non-volatile line; and circuitry that,during a program mode, applies an alternated signal to the transfernode, couples the second terminal of the second non-volatile element tothe second non-volatile line, and applies a program signal across thefirst and second non-volatile lines and that, during a restore mode,applies a read signal across the first and second non-volatile lines,couples the second terminal of the second non-volatile element to thesecond non-volatile line, and replaces the alternated signal withfloating, in which a logic state represented the first and secondnon-volatile elements that have been programmed is loaded from thetransfer node to the storage node.
 19. The NVDRAM of claim 18, furthercomprising a pass gate coupled between a bit line and the storage nodethat is used to couple the bit line to the storage node that enablesreading the logic state.